We are hiring an experienced FPGA / RTL implementation lead to help drive the development of Ludwig’s first hardware acceleration platform.
We are looking for a technically exceptional and highly practical engineer who can translate a broader hardware architecture into a staged FPGA implementation plan: concrete module boundaries, interfaces, validation milestones, bring-up steps, and realistic development timelines. The ideal candidate is comfortable moving between system-level architecture, RTL design review, FPGA bring-up planning, and performance analysis.
You will work directly with the founding team to make the FPGA implementation path more deterministic: defining what needs to be built, sequencing the work, assigning well-scoped technical tasks, reviewing progress, and helping the team converge toward a working prototype. This role requires someone who can provide strong technical direction while still being close enough to the RTL to review designs, debug critical issues, and contribute directly to high-risk or blocking pieces when needed. A central part of the role is breaking down complex hardware goals into implementable blocks, identifying risks early, guiding verification strategy, and helping the team make steady progress toward working hardware.
This is a senior technical leadership role at the intersection of FPGA systems, RTL design, hardware acceleration, and hardware-software co-design. Engineers excited by early-stage environments, high-performance compute, and turning ambitious hardware architectures into executable engineering plans and measured FPGA results are encouraged to apply.