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ASIC STA Engineer
Job Title
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Full Name
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Phone Number
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Email Address
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Total Experience
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Relevant Experience
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Have you independently debugged simulation/regression failures and identified root causes in RTL or UVM testbench environments?
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A
Yes
B
No
Do you have hands-on experience in both Pre-Layout & Post-Layout STA and Timing Closure?
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A
Yes
B
No
Do you have hands-on experience with SDC constraints and MMMC analysis across Functional/DFT modes?
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A
Yes
B
No
Have you used Synopsys PrimeTime and/or Cadence Tempus for STA/timing sign-off?
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PrimeTime
Tempus
Both
Neither
How many ASIC/SoC tape-outs have you supported in STA/timing sign-off?
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Current Company
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Current Designation
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Current CTC
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Expected CTC
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Notice Period
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Offers in Hand
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Interested In
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Current Location
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Preferred Location
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Submitted By
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